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| order number: MS140132KT/d rev. 1, 5/2001 ? motorola, inc., 2001. all rights reserved. semiconductor products sector this document contains information on a new product. specifications and information herein are subject to change without notice. advance information 6kruw+dxo/rrs'xdo3&0 &rghf)lowhu6/,&&klsvhwzlwk 63,,qwhuidfh MS140132KT
MS140132KT iii &217(176 section 1 overview 1.1 introduction: mc1420233 codsp and mc1430132 shlic. . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 section 2 applications 2.1 recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 section 3 pin descriptions 3.1 device pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 mc1420233 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 mc1430132 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1 codsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.2 shlic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.5 note on decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5.1 codsp decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5.2 shlic decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 section 4 functional characteristics of the sh-pots system 4.1 on-hook conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 ringing injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1 balanced ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -3 4.2.2 semi-unbalanced ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 battery voltage and reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 MS140132KT iv contents 4.4 ac transmission characteristics (MS140132KT system). . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4.1 transmit and receive filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4.2 transmit and receive gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.3 source impedance (z co ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.4 balance impedance (echo canceller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5 metering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5.1 metering injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5.2 metering characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 0 4.6 tone generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.7 codsp clock recovery pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 section 5 electrical characteristics 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 thermal shutdown shlic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.1 transient energy capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 dc characteristics (mc1430132 shlic, unless otherwise noted) . . . . . . . . . . . . . . . . . . . . 5-2 5.4.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4.2 v dd3 regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.3 dco dc levels, impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.4 vag analog ground input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.5 dc loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7 5.4.6 dcc input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7 5.4.7 characteristics for the digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4.8 test switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.9 battery switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 5.5 ac characteristics (shlic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.1 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.5.2 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.5.3 overpower and short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6 off-hook characteristics (MS140132KT system) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.7 off-hook detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.8 programming the pcm clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 section 6 detailed programming description 6.1 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 functional description of the programming interface: spi . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.4 programmability of the sh-pots chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.4.1 software reset of the chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 v MS140132KT contents 6.4.2 control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 6.4.3 access to the codsp memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5 id request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.6 read request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.7 write request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.8 programming other features via the spi interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.8.1 write spi interface memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.8.2 read spi interface memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.9 idle command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.10 registers in the spi interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.11 programming the pcm interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.12 memory map of the codsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.13 data ram memid = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -13 6.14 lbo register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.15 alarm bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.16 meaning and default values of the parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.17 coprocessor coefficient ram memid = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.18 meaning and default values of the parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.19 shared memory memid = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -21 6.20 meaning and default values of the parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 section 7 mechanical specifications 7.1 mc1420233 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 1 7.2 mc1430132 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 2 7.3 recommended pad layout for 44-lead tqfp mc1420233 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 MS140132KT vi ),*85(6 1-1. block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2-1. typical sh-pots application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2. application schematic for two analog lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-3. recommended overvoltage protection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 3-1. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2. mc1420233 codsp recommended power-supply decoupling arrangements . . . . . . . . . . . . 3-7 4-1. sh-pots line voltages example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2. nominal hookswitch detection thresholds (default values) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-3. application suggestion for semi-unbalanced ringing injection . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-4. dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-5. transmit and receive frequency response (default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-6. relative group delay, transmit and receive paths (digital-to-digital) referred to 1 khz . . . 4-7 4-7. three-element z co model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-8. metering pulse timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 5-1. block diagram showing gains in various signal paths in shlic . . . . . . . . . . . . . . . . . . . . . . 5-10 5-2. short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5-3. write signalling register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 6-1. spi bus timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-2. pcm bus timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-3. software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6-4. write control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-5. id request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-6. read request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-7. write request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-8. register write request types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-9. register read request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-10. timing example of pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 7-1. recommended pad layout for 44-lead tqfp mc1420233 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 MS140132KT vii 7$%/(6 2-1. recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 3 3-1. pin descriptions for mc1420233 codsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2. pin descriptions for mc1430132 shlic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-3. mc1420233 codsp unused pin connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-4. mc1430132 shlic unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 4-1. on-hook characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2. ringing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-3. dc feed characteristics [r feed = 60 w total (50 w +10 w protection) x 2] . . . . . . . . . . . . . . 4-5 4-4. examples of z co coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-5. metering characteristics (determined by mc1420233 codsp) . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-6. tone signal levels (common values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -11 4-7. tone generator division values for common frequencies from ets-300-001 and dtmf tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-8. required frequency setting values (n) for a melody generator (western equal-tempered scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -13 5-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2. operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-3. power supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-4. shlic dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-5. power-on reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-6. v dd3 regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-7. voltage characteristics a wire (aw), b wire (bw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5-8. impedance characteristics a wire (aw), b wire (bw). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5-9. rx, tx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-10. dco characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-11. vag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-12. dc loop filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-13. dcc input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-14. digital i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5-15. sense bridge inputs characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5-16. test switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-17. ringing battery switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-18. typical gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-19. short circuit protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5-20. off-hook characteristics (MS140132KT system) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 MS140132KT viii tables 6-1. spi bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-2. pcm bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-3. memory map: spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6-4. memory map for codsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-5. data ram: memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-6. lbo register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-7. data ram: description and default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6-8. coprocessor coefficient ram: memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6-9. coprocessor coefficient ram: description and default values . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6-10. shared memory: memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 6-11. shared memory: description and default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 MS140132KT 1-1 6(&7,21 29(59,(: ,1752'8&7,21 0&&2'63$1' 0&6+/,& the MS140132KT chipset provides all the functions necessary to connect analog telephone sets or other analog terminals (telefax, answering machines, modems, etc.) into digital communication systems. it provides an economical solution for the traditional bors(c)ht [battery, overvoltage, ringing, supervision, (codec), hybrid, test] functions found in central-office exchanges, but is optimized for short-range communication [e.g., up to 500 m with 5 rens (ringer equivalence number) attached]. virtually all system-dependent parameters can be set under software control, giving an unprecedented flexibility to the system integrator, as well as optimizing the system cost. the digital interface to the sh-pots (short haul, plain old telephone system) chipset uses the pcm/spi interface. the system architecture has been designed to offer the most cost-effective solution for short haul systems, yet offers the full flexibility required to meet worldwide analog telephony standards. the MS140132KT chipset is also suitable for q.552 applications. the MS140132KT chipset comprises three devices (see figure 1-1): a pair of high-voltage devices, the short haul line interface circuit (shlic) which provides the signal and power interface to the analog lines (one per line), and a low-voltage cmos, dsp-based dual codec/control device (codsp) which provides all signal processing and control functions for up to two lines. .(<)($785(6 ? digitally programmable transmission and signalling characteristics meet worldwide specification requirements ? integrated ringing: sine or trapezoid with auto cadence ? metering injection (12 or 16 khz) ? support on-hook transmission: adsi, clip ? battery reversal ? codec and ac parameters (z co and hybrid) are fully programmable (a-law or m -law) ? tone generators for signalling and testing ? loop current control and monitoring are programmable ? minimal external components ? codec and slic functions for two lines MS140132KT 1-2 overview: key features ? low-cost pots interface for short range ? flexible idl interface with timeslot assigner ? test support (test load switch, loopback, tone generators) ? supports up to C72 v on v bat ring and C35 v on v bat speech ? codsp (dual codec) is 3.3 v with 5 v tolerant input for low power consumption ? pcm interface with clock frequency from 512 khz to 8192 khz in steps of 512 khz, programmable up to128 channels for speech ? spi interface with clock frequency up to 8192 khz to control the pcm and sh-pots functions ? one programmable output per line for signaling (default: off-hook detection) figure 1-1. block diagram det0 det1 current codsp (with change of pins) spi registers busy spi interface pcm interface ch0 spi in ch1 spi out spiclk pcm out pcm in pcma pcmclk frame MS140132KT 2-1 6(&7,21 $33/,&$7,216 figure 2-1 shows a typical sh-pots application using motorola semiconductor chip solutions. the short haul dual pcm chipset provides all necessary functions to connect analog telephone sets or fax terminals to digital communications systems. ? advanced isdn nt (ntplus), smart nt1 personal router ? analog/digital pabx ? cable telephone systems (set-top box) ? remote telephone access systems fiber to the curb radio in the loop ? internet telephones figure 2-1. typical sh-pots application metallic terminator transceiver flash mc145572 u mc145574 s/t scp pcm dram pots circuitry MS140132KT scp scc1 scc2 scc3 timer bus interface gpio 68030 cpu core ethernet mac ethernet transceiver ethernet 10base-t analog pots/fax "u" or "s/t" interface dc MS140132KT 2-2 applications: shlic shlic codsp d p bats batr v dd5a v ssb dclf1 rx tx dcc dco dci v bats v batr v dd5a c dci c pll dclf2 v ssa sa aw ssb bw sb tst br rng pu bat c f1 c f2 r f1 r f2 r prot tst[0] br[0] rng[0] pu[0] c b1 c b2 tx[0] dcc[0] tst br rng pu batr v dd5a v ssb dco[0] sa aw v d d 3 vag cv3a protection cv3d rb2 rb1 rx[0] vag rb1 tst[1] br[1] rng[1] pu[1] rx[1] tx[1] dcc[1] dco[1] cpll v ssd c pwrs pwrs r pwrs v ssa v bats z test v dd3d spi in spi out busy pcm out ch0 ch1 pcmclk frame pcm port r prot jtdi jtdo jtck jtms jtrs det1 jtag test access device test v dd3a c b2 rb2 z test b spiclk protection v dd3d 0 0 0 1 1 r f1 r f2 d1 1 v dd3 a b dclf1 dco dci vag a det0 dclf2 v ssa d p v batr v dd5a pcm in c vag c dci ssb bw sb bats rx tx dcc bat c f1 c s c d d p c b1 c f2 line line figure 2-2. application schematic for two analog lines c p c d c s c p spi port 2-3 MS140132KT applications: recommended external components 5(&200(1'('(;7(51$/ &20321(176 29(592/7$*(3527(&7,21 there are several recommended overvoltage protection options. the application will determine the most appropriate one to chose (e.g., in-house only systems with minimal protection requirements, or systems with loops outside a protected environment requiring more extended protection). the first external protection network to protect the line circuit against foreign voltages consist of resistors r pr1 and r pr2 and an overvoltage protection component (see figure 2-3). series resistors r pr1 and r pr2 can be ptc, poly-switch, or fusible components. for further protection, the simplest and cheapest solution is a diode bridge between sa, sb and v ssb , batr, respectively. the diodes must be able to allow current peaks more than 20 a. in case the battery batr can not accept these high current peaks, add a voltage clamping component to v ss , or a transient suppressor between each line and v ss . the clamp voltage or protection voltage minimum must always be larger than the maximum used ringing battery batr. table 2-1. recommended external components component function x comment r b1 , r b2 feed resistor 50 w 1/4 w 1% (see note 1) r prot protection resistance 2 x 10 w z test test resistor 510 w 1/4 w, optional r f1 , r f2 dc bias filter 10 k w c b1 , c b2 no-load stabilization 1 nf 100 v (see note 2) c dci dc feed separation 330 nf 5% c f1 , c f2 dc bias filter 470 nf 100 v, 10% c vag analog ground decoupling 100 nf cv3a analog 3.3 v regulator decoupling 10 m f + 100 nf cv3d digital 3.3 v decoupling 10 m f + 100 nf c s battery supply decoupling 100 nf 100 v c pll pll loop filter 4.7 nf c pwrs power-on reset delay 100 nf r pws power-on reset delay 100 k w d 1 power loss reset any small signal diode d p battery input protection bat46 required depending on the power supplies c d 5 v power supply decoupling 100 nf notes: 1. a 1% results in a maximum longitudinal balance of 40 db. for higher values, more precise matching is required (e.g., 0.1% for 46 db). 2. capacitors are generally not required. they are foreseen to stabilize the line driver outputs when active but driving no load (test condition only). MS140132KT 2-4 applications: overvoltage protection the protection components must be dimensioned in such a way that the transient energy on the chip pins aw, bw does not exceed 1 mjoule (or, the energy on-chip because of one lightning pulse). batr aw sa sb bw mc1430132 shlic rb2 v ssb aw sa sb bw mc1430132 shlic rb1 v ssb aw sa sb bw mc1430132 shlic v ssb aw sa sb bw mc1430132 shlic figure 2-3. recommended overvoltage protection options transient suppressor v ssb r pr2 r pr1 r pr2 r pr1 rb1 rb2 rb1 rb2 r pr2 r pr1 r pr2 r pr1 rb1 rb2 MS140132KT 3-1 6(&7,21 3,1'(6&5,37,216 '(9,&(3,12876 pwrs busy det0 det1 spi out pu[0] rng[0] br[0] tst[0] test z out spiclk spi in ch0 ch1 tst[1] br[1] rng[1] pu[1] sclk pllck cpll 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 pin 1 indicator rx[0] tx[0] dcc[0] dco[0] dcc[1] dco[1] v ssa vag v dd3a tx[1] rx[1] jtdo jtck jtms jtdi jtrs v dd3d pcm out pcm in pcmclk frame v ssd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 aw sa sb ssb dco dci nc nc dcc tx rx dclf1 dclf2 v dd3 v ssb bw bat bats batr pu nc nc rng br tst vag v dd5a v ssa mc1420233 44-lead tqfp mc1430132 28-lead soic figure 3-1. pin assignments MS140132KT 3-2 pin descriptions: mc1420233 pin descriptions 0&3,1'(6&5,37,216 table 3-1. pin descriptions for mc1420233 codsp pin name pin no. pin description type (see note) jtdo 1 jtag test port data out do jtck 2 jtag test port clock diu jtms 3 jtag test port mode select diu jtdi 4 jtag test port data in diu jtrs 5 jtag test port reset diu v dd3d 6 digital section supply voltage p pcm out 7 three-state pcm transmit data output that is enabled based on frame do5 pcm in 8 pcm receive data input, which is shifted into the codsp following a programmed delay on the frame leading edge di5 pcmclk 9 2.048 mhz clock input di5 frame 10 transmits and receives frame sync pulse for line 0 di5 v ssd 11 digital ground (0 v) p spiclk 12 2.048 mhz control clock input di5 spi in 13 bit serial data input di5 ch0 14 line 0 select, when ch0 = 0, the spi out returns the data and the 8-bit control and programming data can input to the codsp to control line 0 via spi in , when ch0 goes from low to high, the data is latched di5 ch1 15 line 1 select, same functionality as ch0 di5 tst[1] 16 shlic 1 test select do br[1] 17 shlic 1 bat reverse control do rng[1] 18 shlic 1 ring control do pu[1] 19 shlic 1 power-up control db sclk 20 system clock (test only) di pllck 21 pll clock (test only) dis cpll 22 pll loop filter capacitor ao rx[1] 23 shlic 1 rx analog signal ao tx[1] 24 shlic 1 tx analog signal ai v dd3a 25 analog supply voltage p vag 26 analog ground reference voltage output ao v ssa 27 analog ground (0 v) p dco[1] 28 shlic 1 dc loop output ai dcc[1] 29 shlic 1 dc loop control ao 3-3 MS140132KT pin descriptions: mc1420233 pin descriptions dco[0] 30 shlic 0 dc loop output ai dcc[0] 31 shlic 0 dc loop control ao tx[0] 32 shlic 0 tx analog signal ai rx[0] 33 shlic 0 rx analog signal ao z out 34 digital i/o drive control (test only) db test 35 test mode select (test only) did tst[0] 36 shlic 0 test select do br[0] 37 shlic 0 bat reverse control do rng[0] 38 shlic 0 ring control do pu[0] 39 shlic 0 power-up control db spi out 40 bit serial data output do5 det1 41 on/off hook and ring trip detection output (line 1) do5 det0 42 on/off hook and ring trip detection output (line 0) do5 busy 43 indicates when a command is being executed do5 pwrs 44 reset input dis note: the first letter differentiates between: d: digital a: analog p: power the second letter differentiates between: i: input o: output b: bidirectional the third letter differentiates between: d: pin with internal pull-down u: pin with internal pull-up s: pin with schmitt-trigger input 5: 5 v compatible input nc: no connect table 3-1. pin descriptions for mc1420233 codsp (continued) pin name pin no. pin description type (see note) MS140132KT 3-4 pin descriptions: mc1430132 pin descriptions 0&3,1'(6&5,37,216 table 3-2. pin descriptions for mc1430132 shlic pin name pin no. pin description type v ssb 1 battery ground (0 v) p bw 2 b wire output ab bat 3 battery voltage (output, do not connect) p bats 4 battery voltage input, speech mode p batr 5 battery voltage input, ring mode p pu 6 power-up control di nc 7 do not connect; thermal conduction pin nc nc 8 do not connect; thermal conduction pin nc rng 9 ring mode control di br 10 battery reverse control di tst 11 test mode control di vag 12 analog ground reference input p v dd5a 13 analog supply voltage p v ssa 14 analog ground, 0 v p v dd3 15 3 v regulator output p dclf2 16 dc bias filter capacitor 2 ao dclf1 17 dc bias filter capacitor 1 ao rx 18 analog receive signal ao tx 19 analog transmit signal ai dcc 20 dc loop control input di nc 21 do not connect; thermal conduction pin nc nc 22 do not connect; thermal conduction pin nc dci 23 dc loop control separation filter input ai dco 24 dc loop control output ao ssb 25 loop test resistor switch ai sb 26 b wire sense input ai sa 27 a wire sense input ai aw 28 a wire output ab notes: 1. a 1% results in a maximum longitudinal balance of 40 db. for higher values, more precise matching is required (e.g., 0.1% for 46 db). 2. capacitors are generally not required. they are foreseen to stabilize the line driver outputs when active but driving no load (test condition only). 3-5 MS140132KT pin descriptions: unused pins 8186('3,16 &2'63 table 3-3 lists the pins on the codsp that are not connected. pins that are not used in the application should be connected as described here. failure to do so could result in excessive sensitivity to rfi or other erratic behavior. a 0 or 1 indicates that the pin should be connected to ground or to the devices digital supply. a indicates that the pin is an output and must be left unconnected. 6+/,& table 3-4 lists the pins on the shlic that are not connected. the nc pins (7, 8, 21, and 22) are connected to the device substrate, which is at a voltage equal to the v batr supply pin, and may optionally be electrically connected to this pin. table 3-3. mc1420233 codsp unused pin connections pin name pin no. connect to jtdi 4 1 (v dd3d ) jtdo 1 jtck 2 1 (v dd3d ) jtms 3 1 (v dd3d ) jtrs 5 0 (v ss ) sclk 20 v ss pllck 21 v ss z out 34 v ss test 35 v ss table 3-4. mc1430132 shlic unused pin connections pin name pin no. connect to bat 3 no connect or see text above nc 7 no connect or see text above nc 8 no connect or see text above nc 21 no connect or see text above nc 22 no connect or see text above MS140132KT 3-6 pin descriptions: note on decoupling the bat pin is the internal supply to the line drivers, and adopts the voltage of v batr or v bats , plus the voltage drop across the internal switch, depending on the operating mode. in low-voltage only systems (very short connections), the bat pins, v batr and v bats , may all be connected together and a single supply (e.g., C27 v) may be used for both ringing and speech modes. (in this mode, the voltage drop of the internal switches is avoided.) 127(21'(&283/,1* as in any system, the pcb layout and supply decoupling can influence the system performance, particularly with respect to noise. &2'63'hfrxsolqj ? it is recommended to connect v dd3d and v dd3a (digital and analog supply pins) in a star configuration from the supply (either from the shlic or from an external supply), and each pin be independently decoupled using 10 m f in parallel with 100 nf. in two-line systems, using the shlic regulator to supply only the codsp (i.e., no other use is made of the regulator), one shlic may be used to provide v dd3d power and the other v dd3a , thus giving improved decoupling between analog and digital supplies. see figure 3-2. ? the vag line (analog signal reference) must always be properly decoupled using 100 nf, placed as close as possible to the codsp device. 6+/,&'hfrxsolqj ? the shlic should use separate 100 nf decoupling capacitors between v dd5a and v ssb , and v dd5a and v ssa . when the on-board regulator of the shlic is not used, no capacitor is required at the v dd3 pin. 3-7 MS140132KT pin descriptions: note on decoupling figure 3-2. mc1420233 codsp recommended power-supply decoupling arrangements mc1430132 shlic mc1420132 codsp v ssd v dd3d v ssa v dd3a vag +3.3 v star point ground star-point v ssa v ssb v ssa v ssb v ssa 10 m f t a 100 nf mc1430132 shlic mc1430132 shlic mc1430132 shlic mc1420132 codsp v ssd v dd3d v ssa v dd3a vag ground star-point v ssb v ssa 10 m f t a 10 m f t a ceramic ceramic 100 nf ceramic 100 nf 100 nf ceramic v ssb v dd3 v dd3 100 nf ceramic 10 m f t a (b) arrangement b (a) arrangement a 100 nf ceramic MS140132KT 4-1 6(&7,21 )81&7,21$/&+$5$&7(5,67,&62)7+( 6+32766<67(0 for reference, figure 4-1 shows the typical voltages on tip and ring during various stages of operation. for detailed electrical parameters, refer to section 5. 21+22.&21',7,216 when a line is not in use (on-hook), the designer may select either the speech battery or the ringing battery as the supply to the line drivers. in the on-hook mode, most of the internal circuits are put into a low-power operating mode to minimize supply currents. the a and b wire outputs are effectively connected to the supply voltage, thus applying this voltage (minus a small saturation voltage) to the line. the output is current-limited in this mode, thus protecting against short circuits and limiting any inrush current when a set goes off-hook. if the shlic detects a current in excess of a (programmable) limit, the off-hook 0 v v bats v batr on-hook (saturation, <0.5 v) (e.g., C24 v) (e.g., C64 v) (bias, 3 v + drop of bat switch) (bias, 3 v + drop of bat switch) figure 4-1. sh-pots line voltages example on-hook adsi ring burst off-hook (bias, 3 v) (bias, 3 v) (avg. dc = v batr /2) 4-2 MS140132KT functional characteristics of the sh-pots system: on-hook conditions condition will be detected (an on-chip debouncer with selectable delay avoids accidental hookswitch detection), and the circuit will be put into active speech mode. the nominal off-hook detection currents and hysteresis are shown in figure 4-2. when a line is in the on-hook condition, the system designer may select, under program control via the pcm/spi bus, an on-hook active mode, whereby, on-hook signalling (adsi, clip, etc.) can be performed in either direction (though battery reversal is not available in this mode). the hookswitch detector has a programmable debounce timer. times of 8, 16, 24, or 64 ms can be selected. (the timer is common for both channels.) notes: 1. i line = 0 ma, independent of battery reversal mode. this voltage is selected by the user. the output impedance when in the on-hook condition is set by the sense resistors r feed . the hook-switch detector has a programmable debounce timer. times of 8, 16, 24, or 64 ms can be selected (common for both channels). 2. these are the default values after reset. the on-hook and off-hook thresholds can be individually programmed in the range 0 to 63 ma nominal. 3. this is the intrinsic current limit of the output driver. this current can only be seen during on-hook to off-hook transients, or during ringing into a short-circuit load during the ring-trip delay period. the actual value measured will depend on the load resistance used. table 4-1. on-hook characteristics parameter condition min max unit note v feedo open-line feed voltage v bats-1 v batr-1 v1 i on line current guaranteeing on-hook state 4.67 7.93 ma 2 i off line current guaranteeing off-hook state 7.86 12.14 ma 2 i ohyst hookswitch detect hysteresis 2 ma2 i oc peak over-current limit, on-hook mode 145 ma 3 v biash v biasl bias voltage during adsi mode on a (h) and b (l) wires, ref. bat pin 24v off-hook on-hook line current (ma) figure 4-2. nominal hookswitch detection thresholds (default values) 6.3 10.0 MS140132KT 4-3 functional characteristics of the sh-pots system: ringing injection 5,1*,1*,1-(&7,21 %dodqfhg5lqjlqj the sh-pots chipset is capable of directly injecting a ringing signal of up to 50 vrms (sine wave) without the need for additional external components. the technique of balanced ringing is used, which allows this large voltage swing to remain within the technology limits of the shlic device. (balanced ringing requires a specific algorithm for ring-trip detection, which is also implemented by the chipset.) the sh-pots chipset allows the user to program a dc offset during ringing as well as a reduced amplitude ringing signal, should the application require this. ringing waveform, frequency, amplitude, and cadence, as well as ring-trip thresholds, are controlled by the codsp device, and are all programmable. ringing cadence can be automatic, with independently programmable ring and pause times, or ringing can be controlled directly via the pcm/spi bus. in the automatic cadence mode, ringing bursts on both channels can be optionally interleaved, if simultaneously active, to avoid peaks in current from the ringing battery supply. notes: 1. ringing voltage is user-programmable from 0 to 70 vp(diff) between the a and b wires (nb, the ringing battery voltage must be large enough to encompass this voltage) in 256 steps. the default is the maximum value. condition: load = 0 ma. 2. user-selectable 0 or 30 ms. default is 30 ms. 3. these are the default values after reset. the max and min ring-trip thresholds can be individually programmed in the range 0 to 63 ma nominal. the ring-trip detect mask time is used to bridge the zero-crossings of the ringing signal, and is programmable between 0 and 32 ms in 125 m s steps. 4. units are periods of the selected ringing frequency. the default values are 1 s on, 3 s off, with a ringing frequency of 50 hz. table 4-2. ringing characteristics parameter condition min max unit note f r ringing frequency 16.66, 20, 25 hz 50 hz C1 C2 1 2 hz sf nr single-frequency noise, 10 hz to 4 khz C63 dbm v r ringing voltage (max), v batr = C72 v 50 vrms 1 d r ringing distortion, sine mode 30 hz to 132 khz 5 % t rtd ring-trip delay, load = 500 w + 4 m f 150 ms t rtdeb ring-trip debounce time 0 30 ms 2 t c ring-cadence times (active and silent) 1 255 n/n 4 i rth ring-trip current, high threshold 6.0 12.0 ma 3 i rtl ring-trip current, low threshold 3.5 9.5 ma 3 h rt ring-trip hysteresis 2 ma 3 4-4 MS140132KT functional characteristics of the sh-pots system: dc feed characteristics 6hpl8qedodqfhg5lqjlqj in order to support semi-unbalanced ringing (dc bias equal to v batr superimposed on the differential ringing signal), two of these outputs will be active high during the active ringing period on each channel (spick for channel 0 and spics for channel 1). this can be used to drive a relay via an external npn transistor, as shown in figure 4-3. '&)(('&+$5$&7(5,67,&6 as shown in figure 4-4, the sh-pots chipset implements a constant-current feed. the limit current and the residual resistance (slope of the characteristic) are both programmable by the user. the dc characteristic falls into three regions. when the combination of line and subset result in a current less than the programmed limit current, the system behaves like a battery with a fixed feed resistance of 120 w , and a voltage equivalent to the speech supply voltage (v bats ) minus the bias voltage on both lines (6 v nominal in total). should line conditions permit a current that exceeds the programmed limit current, the system enters the constant-current feed mode described above. in order to protect the output stage in the transition region at higher line currents (in excess of 50 ma), a third region is defined, where the system synthesizes a fixed feed resistance of 200 w . the slope of the voltage/current characteristic in the constant-current mode can be user-programmed to select the effective feed-resistance. 127( the shlic device includes over-temperature protection, that activates at 165 c in case of overheating of the device. aw bw r feed r feed protection v batr 47 m f nc rly rly +5 v spick (line 0) or spics (line 1) figure 4-3. application suggestion for semi-unbalanced ringing injection nc line rly MS140132KT 4-5 functional characteristics of the sh-pots system: dc feed characteristics %dwwhu\9rowdjhdqg5hyhuvdo the open-line voltage (i.e., the voltage seen on the line when on-hook) is user-selectable for each channel via an internal register. it can be either the ringing battery supply (most common use) or the speech battery supply. the speech battery supply is automatically selected when an off-hook condition is detected, independently of these control bits. the selected supply voltage is maintained when the on-hook signalling function (adsi) is enabled. the polarity of the line feed can be dynamically controlled by the user. in the normal condition, the a wire is the most positive. thus, reversal makes the b wire the most positive. battery reversal is fast (audible), is controlled by programming an internal register, and is independent for both channels. the selected polarity is used in all states (on-hook, off-hook, ringing, etc.) except for on-hook signalling, which is in normal battery mode. table 4-3. dc feed characteristics [r feed = 60 w total (50 w +10 w protection) x 2] parameter condition min max unit v biash bias voltage, a wire (i line = 0) 2.5 3.5 v v biasl bias voltage, b wire (i line = 0) 2.5 3.5 v tol icl current limit tolerance C15 15 % t rfeedcl tolerance on programmed r feed when in current-limit C15 15 % i cl current-limit, useful programmed range 20 70 ma i line (ma) 20 40 60 80 v line (v) (programmable) r feed r feed = 200 w r feed = 120 w figure 4-4. dc feed characteristics v bats v fn 4-6 MS140132KT functional characteristics of the sh-pots system: ac transmission characteristics (MS140132KT system) $&75$160,66,21&+$5$&7(5,67,&6 06.76<67(0 7udqvplwdqg5hfhlyh)lowhu&kdudfwhulvwlfv the sh-pots chipset implements transmit and receive filters according to itu-t (g.712). these filters can be reprogrammed by the user for specific requirements. please contact a motorola sales office for more information. the implemented default filter characteristics are shown in figures 4-5 and 4-6. 16,000 3,400 3,000 receive transmit C0.3 0.0 0.35 0.55 0.75 1.0 1.5 12.5 25.0 4,000 figure 4-5. transmit and receive frequency response (default) 12.5 1200 receive / transmit 200 300 400 600 2,400 3,600 4,600 p (4000C?) 1 C sin db [] (db) (hz) frequency MS140132KT 4-7 functional characteristics of the sh-pots system: ac transmission characteristics (MS140132KT system) 7udqvplwdqg5hfhlyh*dlq transmit (from analog subset towards the switching system) and receive gains are user-programmable, independently for both lines. the default values are 0 dbr in the transmit direction, and C7 dbr in the receive direction. 6rxufh,pshgdqfh = &2 the central-office impedance, z co , is synthesized using digital signal processing techniques. this renders it very stable, and moreover, programmable by the user by means of coefficients which are loaded via the pcm/spi. real or complex z co impedances can be synthesized using the common three-element model (rs, rp, cp; see figure 4-7). the z co setting is common for both lines. both real and complex z co impedances can be programmed to address the local requirements of specifications worldwide, and cover the following range. using the default coefficient values, the return loss when measured against 600 w (using 0 dbm input signal level) is better than 20 db in the 300 to 3400 hz band, and better than 10 db at 10 khz. real impedances: 600 w to 900 w . complex impedances: rs from 160 w to 500 w rp from 300 w to 1000 w rp//cp pole from 725 hz to 5 khz. 1500 1200 900 600 300 0 1800 500 2800 frequency (hz) ( m s) delay figure 4-6. relative group delay, transmit and receive paths (digital-to-digital) referred to 1 khz 2600 2000 1000 600 4-8 MS140132KT functional characteristics of the sh-pots system: metering %dodqfh,pshgdqfh (fkr&dqfhoohu the balance impedance (model of the line plus set impedance used to separate the receive and transmit signals in the hybrid) is independently programmable (though is the same for both channels). default values offer echo return loss of better than 20 db, though optimization to specific line and set characteristics may yield further improvement. 0(7(5,1* 0hwhulqj,qmhfwlrq metering pulses of selectable frequency (12 khz or 16 khz) and programmable amplitude can be injected into either analog channel independently. the width of the injected pulse is determined by the user (on/off mode), or by an internal timer (burst mode) which can be set by the user from 2 ms to 510 ms in steps of 2 ms. the metering signal is always a multiple of half metering periods. see figure 4-8. metering is initiated on a channel by an active low state on the corresponding mpi bit in the pcm/spi c/i byte. table 4-4. examples of z co coefficients rs rp cp z co sh alfa3 z co a2 rz co z co - gamma z co - alfa3 ftx ap nan acg belgium 600 0 0 0 0 3 0 0 237 0 0 103 germany 220 820 115 nf 0 40 9 9 5 52 346 512 125 europe 270 750 150 nf 0 19 7 15 4 122 388 C179 125 z co 850 850 0 0 0 0 0 0 0 282 0 0 123 z co 900 900 0 0 0 0 0 0 0 290 0 0 126 h0 h1 h2 h3 a0 c5 b0 dzd0 dzd1 belgium 4 C22 105 95 0 0 0 1 1 germany C31 48 1 156 0 0 0 0 0 europe 3 C23 118 88 0 0 0 0 0 z co 850 4 C22 105 95 0 0 0 1 1 z co 900 4 C22 105 95 0 0 0 1 1 r s c p figure 4-7. three-element z co model r p MS140132KT 4-9 functional characteristics of the sh-pots system: metering the metering level on the line is set by: v lm = (v gen z m )/(z m + z com ) where: v lm = metering pulse level on the line v gen = set level of the metering generator z m = impedance of the metering load z com = co impedance at the metering frequency. the metering level v gen is selectable from 0 to a maximum level of 230 mvrms (500 m line with z co = 900 w ) in 15 linear steps. the internal tolerance on the metering signal level is 10%. figure 4-8. metering pulse timing diagrams metering mpi on/off mode burst mode t mburst metering mpi 4-10 MS140132KT functional characteristics of the sh-pots system: tone generation 0hwhulqj&kdudfwhulvwlfv notes: 1. tolerance = 0.5%. 2. measured in accordance to itu-t specification 071 (blue book). 3. on 200 w. 4. tolerance = 10%. 5. tolerance = max 6%. 721(*(1(5$7,21 the sh-pots system allows the injection of user programmable tones, independently per channel, for signalling or user test purposes. per channel, a tone comprising two programmable (sine wave) frequencies and programmable amplitudes can be generated (in this way, the most common call-progress and information tones, melody notes, or dtmf tones can be synthesized). the tone signal is added to the speech signal (the user must be aware of possible clipping which may occur if high signal levels are programmed), or the speech signal can also be muted during a tone burst. the tone burst duration is under user control only (the control bits for mute and tone insertion occupy the same register, which simplifies the generation of tone bursts). the amplitude of each frequency within the tone can be independently set from 0 to the maximum level in 256 linear amplitude steps (8-bit value), with n = 63 corresponding to 0 dbm on the line. from this, the line signal level, v tl , for a given gain factor n is given by: v tl = 20 log(n/63) in dbm table 4-5. metering characteristics (determined by mc1420233 codsp) (conditions: refer to section 5.2) parameter condition min max unit note f ml metering frequency, 12 khz 11,940 12,060 hz 1 f mh metering frequency, 16 khz 25,920 16,080 hz 1 sfn1 single-frequency noise, subharmonics for 12 khz, 30 hz to 12 khz for 16 khz, 30 hz to 12 khz C69 C69 dbm0 sfn2 single-frequency noise, mixed products 12 khz, 12 khz to 20 khz 12 khz, 20 khz to 132 khz 16 khz C51 C69 C69 dbm0 n mc in-band noise due to metering signal C60 dbmp 2 n mt transient noise due to metering pulse C35 dbm0 2 thd m metering total harmonic distortion, 30 hz to 132 khz, out of codsp 0.5% d m metering signal distortion at load 5 % 3 v lm metering pulse amplitude, maximum level with z co =900 w , r line =130 w 207 253 mvrms 4 sym m metering symmetry, a and b wires 24 db 5 sfn tx single frequency noise, mixed products, 10 hz to 4 khz, tx path C63 dbm MS140132KT 4-11 functional characteristics of the sh-pots system: tone generation or n = int(63 x 10^(vtl/20) + 0.5) table 4-6 lists values for n, for a range of tone signal levels. the tone frequency is given by: fout = 250 x n / 256 hz, where n is a 16-bit value (thus, n = 1024 yields a tone of 1 khz) or n = int(fout x 256/250 + 0.5) the tone generated has continuous phase if the programmed frequency is changed during the course of a tone (this is not so if the generator is stopped and restarted). tables 4-7 and 4-8 list the values of n required to generate commonly occurring frequencies, and the resulting error. table 4-6. tone signal levels (common values) (see note) dbm n actual error (db) 3 89 3.00 0.00 1.5 75 1.51 0.01 0 63 0.00 0.00 C1.5 53 C1.50 0.00 C3 45 C2.92 0.08 C6 32 C5.88 0.12 C8 25 C8.03 C0.03 C10 20 C9.97 0.03 C15 11 C15.16 C0.16 C20 6 C20.42 C0.42 C30 2 C29.97 0.03 C36 1 C35.99 0.01 note: it is possible to generate tones of very high amplitude. the user must ensure that the amplitude parameter is programmed before the tone is enabled. 4-12 MS140132KT functional characteristics of the sh-pots system: tone generation table 4-7. tone generator division values for common frequencies from ets-300-001 and dtmf tones common signalling frequencies frequency (hz) n actual frequency error (%) 300.00 307 299.805 C0.07 320.00 328 320.313 0.10 325.00 333 325.195 0.06 340.00 348 339.844 C0.05 350.00 358 349.609 C0.11 375.00 384 375.000 0.00 380.00 389 379.883 C0.03 382.50 392 382.813 0.08 400.00 410 400.391 0.10 410.00 420 410.156 0.04 420.00 430 419.922 C0.02 440.00 451 440.430 0.10 450.00 461 450.195 0.04 455.00 466 455.078 0.02 475.00 486 474.609 C0.08 490.00 502 490.234 0.05 500.00 512 500.000 0.00 525.00 538 525.391 0.07 550.00 563 549.805 C0.04 dtmf tones frequency (hz) n actual frequency error (%) 697.00 714 697.266 0.04 770.00 788 769.531 C0.06 852.00 872 851.563 C0.05 941.00 964 941.406 0.04 1209.00 1238 1208.984 0.00 1336.00 1368 1335.938 0.00 1477.00 1512 1476.563 C0.03 1633.00 1672 1632.813 C0.01 MS140132KT 4-13 functional characteristics of the sh-pots system: tone generation table 4-8. required frequency setting values (n) for a melody generator (western equal-tempered scale) octave note frequency (hz) n actual error (%) 2 c 261.626 268 261.719 0.04 (middle-c) 2 c# 277.183 284 277.344 0.06 2 d 293.665 301 293.945 0.10 2 eb 311.127 319 311.523 0.13 2 e 329.628 338 330.078 0.14 2 f 349.228 358 349.609 0.11 2 f# 369.994 379 370.117 0.03 2 g 391.995 401 391.602 C0.10 2 ab 415.305 425 415.039 C0.06 2 a 440.000 451 440.430 0.10 2 bb 466.164 477 465.820 C0.07 2 b 493.883 506 494.141 0.05 3 c 523.251 536 523.438 0.04 3 c# 554.365 568 554.688 0.06 3 d 587.330 601 586.914 C0.07 3 eb 622.254 637 622.070 C0.03 3 e 659.255 675 659.180 C0.01 3 f 698.456 715 698.242 C0.03 3 f# 739.989 758 740.234 0.03 3 g 783.991 803 784.180 0.02 3 ab 830.609 851 831.055 0.05 3 a 880.000 901 879.883 C0.01 3 bb 932.328 955 932.617 0.03 3 b 987.767 1011 987.305 C0.05 4 c 1046.502 1072 1046.875 0.04 4 c# 1108.731 1135 1108.398 C0.03 4 d 1174.659 1203 1174.805 0.01 4 eb 1244.508 1274 1244.141 C0.03 4 e 1318.510 1350 1318.359 C0.01 4 f 1396.913 1430 1396.484 C0.03 4 f# 1479.978 1515 1479.492 C0.03 4 g 1567.982 1606 1568.359 0.02 4 ab 1661.219 1701 1661.133 C0.01 4 a 1760.000 1802 1759.766 C0.01 4 bb 1864.655 1909 1864.258 C0.02 4 b 1975.533 2023 1975.586 0.00 5 c 2093.005 2143 2092.773 C0.01 5 c# 2217.461 2271 2217.773 0.01 5 d 2349.318 2406 2349.609 0.01 5 eb 2489.016 2549 2489.258 0.01 4-14 MS140132KT functional characteristics of the sh-pots system: codsp clock recovery pll &2'63&/2&.5(&29(5<3// the codsp device derives its internal clocks from the pcm/spi input by means of a pll. the pll automatically detects the clock mode in use, and sets the multiplication factor accordingly. the pll loop filter requires an external capacitor as shown in the application schematic. 5 e 2637.020 2700 2636.719 C0.01 5 f 2793.826 2861 2793.945 0.00 5 f# 2959.955 3031 2959.961 0.00 5 g 3135.963 3211 3135.742 C0.01 5 ab 3322.438 3402 3322.266 C0.01 5 a 3520.000 3604 3519.531 C0.01 5 bb 3729.310 3819 3729.492 0.00 5 b 3951.066 4046 3951.172 0.00 table 4-8. required frequency setting values (n) for a melody generator (western equal-tempered scale) (continued) octave note frequency (hz) n actual error (%) MS140132KT 5-1 6(&7,21 (/(&75,&$/&+$5$&7(5,67,&6 $%62/87(0$;,0805$7,1*6 operation of the device at or near these conditions is not guaranteed. sustained exposure to these limits will adversely affect device reliability. note: except special 5 v tolerant i/os of codsp as noted in table 3-1. 23(5$7,1*&21',7,216 operating ranges define the limits for functional operation and parametric characteristics of the device as described in this document, and for the reliability specifications. correct functioning outside of these limits is not implied. total cumulative exposure outside the normal power supply voltage range or ambient temperature under bias, must be less than 0.1% of the normal useful life as defined in table 5-1. table 5-1. absolute maximum ratings parameter symbol min max unit battery voltage batr (ref. to v ssb ) of shlic batr C75 0.5 v battery voltage bats (ref. to v ssb ) of shlic bats C35 0.5 v difference between the batteries batr and bats, batr-bats of shlic dbat C40 0.5 v v dd5a (ref. to v ssa ) of shlic v dd5a C0.5 7 v v ssb (ref. to v ssa ) of shlic v ssb C0.5 0.5 v ambient temperature under bias of shlic t a C40 85 c maximum absolute power dissipation, t a = 85c 1.3 w v dd3a ,v dd3d to codsp v dd3 v ss C 0.3 4 v voltage on any device pin (see note) of codsp v in v ss C 0.3 v dd3 + 0.3 v function temperature under bias of codsp C55 150 c storage temperature t stg C65 150 c lead temperature (soldering 10 s) 300 c 5-2 MS140132KT electrical characteristics: thermal shutdown shlic note: see section 5.4; maximum power dissipation is dependent on maximum ambient temperature. 7+(50$/6+87'2:16+/,& thermal limiting circuitry on chip of the shlic will shut down the circuit at a junction temperature of about 165c. the device should never be run at this temperature. operation above 145c junction temperature might degrade device reliability. thermal resistance = 55c/w typ. 7udqvlhqw(qhuj\&dsdelolw\ during testing, each device termination withstands being shorted to the supply voltages or ground as specified below. the shorting must be limited to 1 s. shorted to v ssa , v dd5a or v ssb : vag, pu, rng, br, tst, t a , dcc, dco, dci, tx to rx shorted to v ssa , v ssb or bats: aw, bw, sa to sb '&&+$5$&7(5,67,&6 0& 6+/,&81/(6627+(5:,6(127(' unless otherwise stated, these characteristics apply for the operating conditions specified in section 5.2. all parameters are explicitly or implicitly tested during production at the operating conditions unless they are marked with an asterisk (*), where they are guaranteed by design. parameters marked with a double asterisk (**) are meant as user information only. tests are performed using an equivalent of the application schematic. table 5-2. operating conditions (all voltages referenced to v ssa = v ssb or v ss = v ssa , as appropriate) symbol parameter limits unit min typ max batr ringing battery voltage C72 C65 C18 v bats speech battery voltage C35 C32 C18 v d bat difference between the batteries batr and bats, batr-bats C40 C35 0 v v dd5a supply voltage shlic (ref. to v ssa )4.7555.5v t range operating temperature range C40 85 c (note) v dd3d v dd3a v dd of codsp (3.3 v 8%) 3.036 3.3 3.564 v MS140132KT 5-3 electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) notes: 1. il is the line current; i.e., these parameters are measured without line current. 2. i v3 is the load current in pin v3. 3. the maximum values in the table are valid for the full battery voltage ranges: C18 v to C72 v for ringing battery batr. C18 v to C35 v for battery bats. (batr must always be the most negative one.) 4. in case of sleep mode activation. see tables 6-5 and 6-7 for programming values. the specifications for power dissipation imply that in ring mode, the active ring phase must at least be four times shorter than the non-active ring phase. the maximum duration of the active ring phase must be below 2 s. 3rzhu2q5hvhw table 5-5 shows the power reset threshold for v dd5a of the shlic. as long as v dd5a is below the reset threshold, shlic is held in power-down, and the output pins aw and bw are high impedance. the codsp uses a separate input pin, pwrs, for system reset at power-up. table 5-3. power supply currents symbol parameter test condition limits unit min typ max i batr batr current (il = 0) power rng = 0 0.35 0.5 ma up rng = 1 3.5 5.0 ma power rng = 0 0.35 0.5 ma down rng = 1 2.5 3.5 ma i bats bats current (il = 0) power rng = 0 3.5 5 ma up rng = 1 3.5 5 ma power rng = 0 1.5 2.5 ma down rng = 1 0.5 ma i vdd v dd current (i v3 = 0) power-up 3 5.5 ma power-down 2.5 4 ma p cc power dissipation of codsp (@ 3.45 v v dd3a and v dd3d ) power-down 30 mw power-up 1 line active* 140 mw power-up 2 lines active 180 mw table 5-4. shlic dissipation parameter symbol value unit maximum operating power dissipation, t a = 70c pmax_op 1.2 w 5-4 MS140132KT electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) 9 '' 5hjxodwru this series regulator of the shlic can be used to provide the supply voltage for the codsp or other 3.3 v devices. table 5-5. power-on reset characteristics symbol parameter test condition limits unit min typ max v ddpwr threshold voltage for power reset on v dd of shlic 3.0 3.5 4.0 v t pwrs active low pulse width on pwrs of codsp 10 ms v pwrs threshold voltage for reset on pwrs of codsp 1.6 1.7 v table 5-6. v dd3 regulator characteristics symbol parameter test condition limits unit min typ max v dd3 v dd3 output voltage load current i v3v between 0 and 50 ma 3.05 3.3 3.55 v i load load current range 0 50 ma psrr signal rejection v dd to v dd3 frequency range 0 to 10 khz 20 db l reg load regulation load current range from 5 to 50 ma C1 1 w c load (**) maximum load capacitance load current range from 0 to 50 ma 100 nf i cc (*) current limitation shorted output v dd3 shorted to v ssa 70 200 ma MS140132KT 5-5 electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) note: these bias values are only valid if both dcc and rx are biased at vag voltage level. table 5-7. voltage characteristics a wire (aw), b wire (bw) symbol parameter test condition limits unit pu br rng min typ max v awn normal dc-bias on aw (ref. v ssb ) 100 C3.5 C3.1 C2.7 v v bwn normal dc-bias on bw (ref. bat) 1002.533.5v v awr reverse polarity dc-bias on aw (ref. bat) 1102.533.5v v bwr reverse polarity dc-bias on bw (ref. v ssb ) 1 1 0 C3.5 C3.1 C2.7 v v aw_h dc bias on aw in act_h mode (tst = 1, ref. v ssb ) 1x1C4C3C2v v bw_h dc bias on bw in act_h mode (tst = 1, ref. bat) 1x1234v v hwpd voltage level high wire (il < 5 ma) 0 x 0 C0.8 C0.5 v v lwpd voltage level low wire (il < 5 ma), ref. bat 0x0 0.50.8v v awring v bwring dc-level both wires in ringing mode (tst = 0) 1 0 1 bat/2 C2% bat/2 bat/2 2% v table 5-8. impedance characteristics a wire (aw), b wire (bw) symbol parameter test condition limits unit min typ max z a(b)wo (*) output impedance at aw (bw) (power-up) 0 ma < il < 70 ma 0 < f < 16 khz 1.5 w z a-bwo (*) tracking of the output impedance on aw and bw 0 ma < il < 70 ma 0 < f < 16 khz 0.3 w z hwod output impedance on high wire (power-down) pu = 0 5 130 w z lwod output impedance on low wire (power-down) pu = 0 5 130 w z omd matching output impedance low versus high wire (power-down) pu = 0 C70 70 w i a(b)oc i a(b)himp output current in and out aw (bw) with ot (over- temperature) detected a(b)w_v ssb and a(b)w_bats C700 700 m a 5-6 MS140132KT electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) '&2'&/hyhov,pshgdqfhv these limits are generally transparent to the user, but are given here for information. 9$*$qdorj*urxqg,qsxw the analog ground is typically half the voltage of the v dd3 output voltage. it is the reference for all analog interfacing between shlic and the codsp. vag is provided by the codsp. table 5-9. rx, tx characteristics symbol parameter test condition limits unit min typ max z tx (*) output impedance at tx f = 1 khz 10 w v otx offset voltage on tx (pu=1) (ref. vag) sa shorted to aw and sb to bw, dci to v dd3 , dco to vag C20 0 20 mv i outtx tx output current capability C1 0.05 ma v rx (*) rx input voltage range (ref. vag) C1 1 v z rx rx input impedance f = 1 khz 20 k w table 5-10. dco characteristics symbol parameter test condition limits unit min typ max z dco (*) output impedance at dco 10 w v odco offset voltage on dco (ref. vag) sa shorted to aw and sb to bw C20 0 20 mv i outdco (*) dco output current capability C1 0.05 ma z dci input impedance at dci f = 1khz 210 k w table 5-11. vag characteristics symbol parameter test condition limits unit min typ max v vag (**) voltage level at vag pin codsp 1.53 1.65 1.77 v i vag vag input current shlic vag = 1.65 v 0.5 ma MS140132KT 5-7 electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) '&/rrs)lowhu these limits are generally transparent to the user, but are given here for information. '&&,qsxw3lq these limits are generally transparent to the user, but are given here for information. note: forcing dcc positive (ref. vag) will result in a smaller voltage between the a and b wire. if too large of a signal is applied at dcc, both wires are clamped at the same voltage (only a small residual voltage remains on the line). table 5-12. dc loop filter characteristics symbol parameter test condition limits unit min typ max v dclf1 dclf1 output voltage (ref. v ssb ) rng = 0, pu = 1 C3.5 C3.1 C2.7 v v dclf2 dclf2 output voltage (ref. bat) rng = 0, pu = 1 2.5 3.0 3.5 v z dclf1s output impedance at dclf, v dclf C v dclf1 < 0.5 v rng = 0, pu = 1 0.6 1 1.4 m w z dclf2s output impedance at dclf, v dclf2 C v dclf < 0.5 v rng = 0, pu = 1 0.6 1 1.4 m w table 5-13. dcc input characteristics symbol parameter test condition limits unit min typ max v dcc dcc input voltage range (ref. vag) rng = 0, pu = 1 C1 1 v i indcc dcc input current, v dcc = vag + 1 v rng = 0, pu = 1 4 10 m a 5-8 MS140132KT electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) &kdudfwhulvwlfviruwkh'ljlwdo,23lqv these include codsp, plus tst, pu, br, rng of shlic. table 5-14. digital i/o characteristics symbol parameter test condition limits unit min typ max v il low-level input voltage 0.8v v ih high-level input voltage 2.0 v i il low-level input current (except pu, see rpd below) v dd = 5.25 v C1 1 m a i ih high-level input current (except pu, see rpd below) v dd = 5.25 v C1 1 m a c inp (*) input capacitance 7 pf r pd pull-down resistance at pin pu 18 30 40 k w v ol output level pu pin, driven low over-temperature ot activated, i pu = 0.2 ma, tested at high temperature only 0.5v v il low-level input voltage, codsp 0.2 x v dd3d v v ih high-level input voltage, codsp 0.8 x v dd3d v v ol low-level output voltage, codsp 0.4v v oh high-level output voltage, codsp 5.25v c in input pin capacitance, codsp (see note) 4pf c out load capacitance, codsp 100 pf i ih high-impedance leakage current v oh = 5.5 v off state C10 10 m a note: excluding package and measured at 0 v. table 5-15. sense bridge inputs characteristics symbol parameter test condition limits unit min typ max r aw-sb bridge resistance from aw to sb v dd , vag = 0 v, 25c 205 257 309 k w r sa-bw bridge resistance from bw to sa v dd , vag = 0 v, 25c 205 257 309 k w MS140132KT 5-9 electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) 7hvw6zlwfk the internal test switch is between pins sb and ssb. connecting an external load between ssb and sa allows test of the transmission characteristics in (simulated) off- and on-hook conditions. the typical on-resistance of the test switch is around 75 w , and has to be taken into account when defining the external load. the test switch is on when rng = 0, pu = 1, tst = 1, br = 0. note: the test switch is normally off when v dd is below the reset level. if the battery voltages are sufficient, the switch remains on, if it was on before v dd went below the reset level. %dwwhu\6zlwfk this switch is activated during ringing or when the higher on-hook voltage is selected (rng = 1). when active, batr is connected to the internal battery supply line v bat . in other cases (rng = 0), the switch is open; v bat is now connected to bats via an internal diode. table 5-16. test switch characteristics symbol parameter test condition limits unit min typ max i swoff switch leakage current |v ssb C vsb| < 72 v 5 m a v swon voltage drop over test switch i sw = 80 ma 4 9 v i sw = 20 ma (v ssb C vsb > 0 v) 13v table 5-17. ringing battery switch characteristics symbol parameter test condition limits unit min typ max i bswoff (*) leakage current battery switch (rng = 0) batr = C72 v, bats = C32 v 5 m a i revbats (*) reverse current bats diode (rng = 1) batr = C72 v, bats = C32 v 5 m a v drbats forward drop bats diode load current < 80 ma 0.85 1.2 v i bson current capability battery switch 080ma v bswon voltage drop over battery switch (rng = 1) load current < 80 ma 1 2 v 5-10 MS140132KT electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) $&&+$5$&7(5,67,&6 6+/,& unless otherwise stated, the characteristic limits apply over the operating conditions specified in section 5.2 and each combination of the drive bits. all parameters are specified in the presence of a longitudinal current of max 5 ma and a dc current of between 0 ma and the current limit. the behavior of the chip in the presence of longitudinal voltages is not tested in production. the different gains in the signal paths are shown in figure 5-1. the values of the gains are given in table 5-18. table 5-18. typical gains gain factor g1 1.66 g1 0.079 g2 2 g3 C2 g4 15 g5 C1/8 gr 1 gr 35/2 (ref. vag) i/o to adsp bw gr g4 g3 g1 g5 bw bias aw v ab sense bridge aw bias g2 rb dcc dco tx rx + + rb zl vl r prot r prot C figure 5-1. block diagram showing gains in various signal paths in shlic MS140132KT 5-11 electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) the gains in table 5-18 are not tested. they are mentioned for information only. the pin-to-pin gains in table 5-20 (g rx , g tx , etc.) are tested and guaranteed. in case of ringing, the receive gain is changed from gr to gr , the transmit gain factor g1 is changed to g1 . the default test condition of the input bits is: pu = 1, rng = 0, br = 0/1. dcc is shorted to vag. note 0 dbm: 1 mw in 600 ohms. 5hfhlyh3dwk the following equation is valid for an open loop configuration. this does not incorporate the z co synthesis, which is defined by the feedback from tx to rx. this function is performed in the codsp. 7udqvplw3dwk the following equation is valid under open loop conditions. 2yhusrzhudqg6kruw&lufxlw3urwhfwlrq in power-down, the dc-loop current limitation is not active. the line current is limited directly through the line drivers. the aw and bw outputs are fully protected against short circuits to a voltage between v ssa /v ssb and batr (see figure 5-2). the current flowing from (or into) aw and/or bw is limited to a value i lw /i hw as long as the junction temperature t j < 165c (electronic current limitation). the values for i lw /i hw for different conditions are given in the table below. if t j rises above 165c (15%) the output drivers outputs are made high impedance. current can only flow in or out of the internal protection diodes, in case v sa and/or v sb exceeds the range between v ss and batr. the currents should, however, be limited externally (internal clamping diodes protection) (see section 2.2). grx vrx = va b = gr(g3 C g2) grx vl = vx = zl 2rb g1 5-12 MS140132KT electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) table 5-19. short circuit protection characteristics symbol parameter test condition limits unit min typ max i lw short circuit peak current, power-up, sink current pu = 1 C145 C120 C95 ma short circuit peak current, power-down, sink current pu = 0 C65 C45 C20 ma i hw short circuit peak current, power-up, source current pu = 1 95 120 145 ma short circuit peak current, power-down, source current pu = 0 204565ma v ssb v ssb batr batr v ssb bw aw v bw v aw rs1 rs2 v sb rs1 = rs2 3 0.3 w figure 5-2. short circuit protection ++ CC v sa MS140132KT 5-13 electrical characteristics: dc characteristics (mc1430132 shlic, unless otherwise noted) 2))+22.&+$5$&7(5,67,&6 06.76<67(0 notes: 1. user programmable. 2. covers variations within the permitted ranges of supply voltage and temperature during any one year. 3. referred to the gain at 1020 hz applied to the input at a level C10 dbm0. 4. intermodulation distortion measured for all intermodulation products of any non-harmonically related frequencies in the range 300 to 3400 hz for levels between C4 and C21 dbm0. 5. intermodulation distortion measured for all intermodulation products of a frequency in the range 300 to 3400 hz at C9 dbm0 and 50 hz at C23 dbm0. table 5-20. off-hook characteristics (MS140132KT system) (conditions: refer to section 5.2) parameter condition min max unit note g tx relative gain, transmit direction gain programming step step accuracy gain tolerance (ref. programmed value) C6 C0.5 1 0.25 0.1 0.5 db 1 g rx relative gain, receive direction gain programming step step accuracy gain tolerance (ref. programmed value) C12 C0.5 1 0.25 0.05 0.5 db 1 d glt long-term gain stability C0.5 0.5 db 2 g ttx gain tracking, tx path 3 to C40 dbm0 C40 to C50 dbm0 C50 to C55 dbm0 C0.3 C0.6 C1.6 0.3 0.6 1.6 db 3 g trx gain tracking, rx path 3 to C40 dbm0 C40 to C50 dbm0 C50 to C55 dbm0 C0.3 C0.6 C1.6 0.3 0.6 1.6 db 3 imd tx intermodulation distortion, tx path C45 dbm0 4 imd rx intermodulation distortion, rx path C50 dbm0 4 s dtx signal to total distortion ratio, tx (gain = 0 db) 0 to C10 dbm0 C20 dbm0 C30 dbm0 C40 dbm0 C45 dbm0 35 34.7 32.9 24.9 19.9 db 5 s drx signal to total distortion ratio, rx (gain = C7 db) 0 to C10 dbm0 C20 dbm0 C30 dbm0 C40 dbm0 C45 dbm0 35 33.8 28.8 19.5 14.5 db 5 sfn rx single frequency noise 300 to 3400 hz, all out-of-band frequencies 700 to 1100 hz in-band 300 to 3400 hz C40 C49 db longitudinal balance 1% 40 db resistor matching 0.1% 46 db 5-14 MS140132KT electrical characteristics: off-hook detection 2))+22.'(7(&7,21 each channel has one i/o pin used for signalling purposes, det* . with this, one signalling bit from the sh-pots chipset can be routed to this output: off-hook detection (ls* ), alarm (al* ), or ring phase (rph* ). register 5 [4-2] defines which bit. det* is the default functionality. this value can be changed as follows. see the ms140131kt/d data sheet for a functional explanation of the signalling bits. the other bits should not be changed. det0 (default) is the on/off hook and ring trip detection open drain output for line 0. when off-hook, det0 goes low. when on-hook, det0 is high impedance. det1 (default) is the corresponding on/off hook and ring trip detection output for line 1. 352*5$00,1*7+(3&0&/2&. )5(48(1&< the pcmclk clock is used for generation of the internal 512 khz clock required for the pcm/spi interface. register 7 has to be programmed to the expected value. spi in 0 1 11 100 output active 0 1 11 100 0 10 x 10 0xx ch* valid combinations: x x x bit to det* pin 100ls* 010al* 0 0 1 rph* figure 5-3. write signalling register MS140132KT 6-1 6(&7,21 '(7$,/('352*5$00,1*'(6&5,37,21 63,,17(5)$&( the data on pin spi in is shifted in on the rising edge of spiclk. the data on spi out occurs at the falling edge of spiclk. the first bit is shifted out on the falling edge of spiclk after ch* became active (= low level) or at the falling edge of ch* after spiclk became active (= low level). the user should ensure that the data on spi out is stable at moment of use: the master device will normally read in the data of spi out on the rising edge of the clock (equal to spiclk on the sh codsp). both select signals ch0 and ch1 can not be simultaneously activated. note that ch* may remain low 8 or 16 bits during shift out of data via spi out depending on the type of read request. MS140132KT 6-2 detailed programming description: spi interface table 6-1. spi bus timing characteristics no. symbol parameter min typ max units 11/t spiclk spiclk frequency 0 2.048 8.192 mhz 2t spiclk_h spiclk high time 50 t spiclk /2 ns 3t spiclk_l spiclk low time 50 t spiclk /2 ns 4t spiclk_r spiclk rise time 15 ns 5t spiclk_f spiclk fall time 15 ns 6t ch_su ch* setup time before spiclk rising edge 50 ns 7t cs_h ch* hold time after spiclk rising edge 50 ns 8t spiin_su spi in data setup time before spiclk rising edge 50 ns 9t spiin_h spi in data hold time after spiclk rising edge 50 ns 10 t spiout_v spi out data valid after ch* falling edge (see notes 1, 2, 4) 0 50 ns 11 t spiout_v spi out data valid after spiclk falling edge (see notes 1 ,2, 4) 0 50 ns 13 t spiout spi out high-z after ch* rising edge (see notes 2, 3) 0 50 ns notes: 1. values guaranteed with a maximum capacitive load of 50 pf. 2. on condition the other pin (= spiclk or ch* ) is already low. 3. when ch* transits to high at the end: bit 0 stays valid until ch* becomes high or next negative transition on spiclk occurs. 4. spi out valid means the moment v ol level is reached for a low level or the moment the driver becomes high impedance (high-z) for a high level. 7 11 7 figure 6-1. spi bus timing parameters 10 11 13 5 9 1 2 3 4 8 6 5 4 3 2 1 1 2 3 4 5 6 spiclk ch0 , ch1 spi in spi out 7 0 0 6 6-3 MS140132KT detailed programming description: pcm interface 3&0,17(5)$&( table 6-2. pcm bus timing characteristics no. symbol parameter min typ max unit 11/t pclk pcmclk frequency ( note 1) 512 2048 8192 khz pcmclk accuracy C100 100 ppm 2t wclkh width of pcmclk high 50 ns 3t wclkl width of pcmclk low 50 ns 4t r pcmclk rise time 15 ns 5t f pcmclk fall time 15 ns 6 frame period 125 ns 7t sfsckl setup time from frame high to pcmclk low 50 ns 8t hckfsl hold time of pcmclk low to frame low 50 ns 9t hckfsh hold time from pcmclk low to frame high 50 ns 10 t sinck setup time from pcm in to pcmclk low 50 ns 11 t hckin hold time from pcmclk low to pcm in invalid 50 ns 12 t dckdxv delay time from pcmclk to pcm out valid (notes 2, 3) 0 50 ns 13 t dcfdxd delay time from pcmclk to pcm out disabled (high-z) 0 50 ns notes: 1. pcmclk must be an integer multiple of 512 khz. 2. pcm out timing is defined with capacitive load = 50 pf. 3. pcm out valid means the moment v ol level is reached for a low level or the moment the driver becomes high impedance (high-z) for a high level. 10 11 13 12 5 figure 6-2. pcm bus timing parameters 6 9 7 1 2 3 4 8 7 6 5 2 1 0 12 0 1 2 5 6 7 pcmclk frame pcm in pcm out MS140132KT 6-4 detailed programming description: pcm interface )81&7,21$/'(6&5,37,212)7+( 352*5$00,1*,17(5)$&( 63, the spi block operates on a totally independent clock, spiclk. this clock can vary from dc up to 8192 khz. if the pin ch0 or ch1 is pulled low (= activation), the clock is gated through the interface block and the other ch* pin is deactivated. with this, the registers of the pcm2gci interface block can be programmed. the data is shifted in via the spi in pin at the rising edge of spiclk. the data is always transmitted as bytes (or multiples). the first byte received via the spi in pin is always the command byte. the first 2 bits define the type of command. these two bits are interpreted on-line and represent a specific action. the table below describes the valid commands, a short functional description and action description from the spi interface block: spi out is a three-state serial data (8-bits, msb first) output. the output is activated at the moment data is available after a gci monitor command (id or read request) or after an interface-block-read request. the data is shifted out of spi out on the spiclk falling edge when ch* is low. at that moment, data on spi in is not accepted by the interface. when both ch* are high, spi out is in high impedance state. before data can be shifted out on spiout, ch* is set high for a small time. the same ch* signal as used for the command must also be used for the data that will be shifted out of spi out . at power-up, the chipset is programmed to power down, and the output spi out is in the high-impedance state (refer also to the memory map). in case multiple bytes are required for execution of a command (e.g., writing data in the codsp memory), these can be send in separate cycles, or within the same activation of ch0 or ch1 . only the command 01* is dependent on which ch0 or ch1 is activated. none of the bytes received via the spi in are echoed via the spi out ; only the requested read-data is returned. b7 b6 function 0 0 software reset 0 1 write control word 1 0 access codec memory 1 1 access interface block registers + idle command valid command function 00000000 software reset 01xxxxxx write control word 10000000 id request 10001bbb write request 10011bbb read request 110yyyyy interface block registers: read request 111yyyyy interface block registers: write request 11111111 idle command: can be used when spi out data is expected 6-5 MS140132KT detailed programming description: programmability of the sh-pots chipset busy function: this signal (when low) indicates that the spi interface is busy with transmitting program data to the required location inside the codsp. the time busy is low depends on the type of command. for example, the control word takes maximum 12 frame periods. when busy is low due to a write of the control word via one channel (ch0 or ch1 ), a control word via the other channel (ch1 or ch0 ) can be written. the commands are executed in the same order as they are programmed. when busy is low, due to execution of a previous command, the user must wait until busy is high again before issuing any new command. 352*5$00$%,/,7<2)7+(6+3276 &+,36(7 the following sections describe how the sh-pots chipset can be programmed. 6riwzduh5hvhwriwkh&klsvhw the software reset unconditionally forces the chipset into the reset state. it can be activated by writing 1 byte via either of the two ch* signals. &rqwuro:rug the control word provides an easy and fast access to the operating states of the chipset. both lines have thier own dedicated control word. the difference is usually chosen by the use of the corresponding ch0 signal for line 0 and ch1 for line 1. it is also possible to address both lines by any ch* signal activation. the control word is a 1-byte command. figure 6-3. software reset spi in execution reset 0 0 0 00 000 ch* MS140132KT 6-6 detailed programming description: id request the bits have following functions. $ffhvvwrwkh&2'630hpru\ the first byte of these commands all begin with b7-6 = 10. (they are exactly the same commands as the ms140131kt sh-pots chipset with gci interface.). the busy signal becomes low after acceptance of the commands (when all required bytes are received) and remain low during execution of the command. when the result is available at the spi out pin, the busy signal becomes high again. ,'5(48(67 there is one required byte. the command returns 2 bytes that are the software revision of the codsp (see explanation in the ms140131kt sh-pots datasheet). the command itself is not echoed. bit activation of when 7 always 0 for control word 6 always 1 for control word 5 tbd (see note) 1 4 tbd (see note) 1 3 polarity reversal 1 2 power-up (adsi mode) 1 1 ringing mode 1 0metering 1 note: bits should always be written 0, foreseen for future extension. figure 6-4. write control word spi in ready for new data x x x 01 xxx ch* busy transfer busy note: activating ch0 or ch1 program the corresponding channel. 6-7 MS140132KT detailed programming description: read request 5($'5(48(67 this is a 3-byte command, which returns 2 bytes; the codec-memory contents at the specified address. the read request is exactly the same as in the sh-pots gci interface description. see explanation in the ms140131kt sh-pots datashee t. the command itself is not returned. figure 6-5. id request spi in start gci transfer 0 0 0 10 000 ch* busy id of codsp spi out gci operation finished figure 6-6. read request spi in ch* busy address spi out address data high high low address high address low data low 1 0 0 1 1 b b b n n n n n n n n n n n n n n n n 1 0 0 1 1 b b b n n n n n n n n n n n n n n n n d d d d d d d d d d d d d d d d MS140132KT 6-8 detailed programming description: write request :5,7(5(48(67 this is a 5-byte command (see explanation in the ms140131kt sh-pots datasheet). 352*5$00,1*27+(5)($785(69,$ 7+(63,,17(5)$&( the spi interface has a memory map in which the setup for the pcm interface can be changed, as well as the clock frequency and the signaling pin. see section 6.12 for a description of the memory map. :ulwh63,,qwhuidfh0hpru\ each address can be written to via the spi interface independently. the command to be used is 111yyyyy + byte to be loaded in the register. the address is defined by yyyyy. it is possible to write more than 1 byte with the same command. for this, the relevant ch* signal has to be pulled low for a multiple of 8 clocks. each time, the byte with the address = previous +1 is written. for valid addresses, see memory map. figure 6-7. write request spi in ch* busy spi out data high address high address low data low 1 0 0 1 1 b b b n n n n n n n n n n n n n n n n d d d d d d d d d d d d d d d d 6-9 MS140132KT detailed programming description: idle command 5hdg63,,qwhuidfh0hpru\ read operation will return the data of the corresponding register. the data is sampled during the bytes following the request, on condition that the idle command is written during the access of the spi interface. ,'/( &200$1' this command is used to read the data from the spi out pin and has no programming effect in the pcm2gcim interface block. ff is returned via spi out if no data is available. figure 6-8. register write request types spi in ch* spi out data latched data add. yyyyy+2 data add. yyyyy 111yyyyy register write request type 1 register write request type 3 (also functional if ch* is not going high) spi in ch* spi out data add. yyyyy 111yyyyy register write request type 2 data latched 111yyyyy data add. yyyyy+x data add. yyyyy+1 data add. yyyyy spi in ch* spi out data latched data latched data latched data latched figure 6-9. register read request spi in data from register yyyyy y y y 11 0yy ch* spi out 1 1 1 11 111 d d d dd ddd idle command MS140132KT 6-10 detailed programming description: registers in the spi interface block 5(*,67(56,17+(63,,17(5)$&( %/2&. there are 11 addressable registers: from 0x05 to 0x0f (hex), and 0x11(hex). these registers are used to control the functions of other interface blocks: pcm interface, gci interface, and clock generator. these registers are controlled by the spi interface. table 6-3 lists the memory map and function. addresses control of: 5 which signaling signal is directed to det* 6 direct c/i bits programming 7 pcmclk frequency 8 C d pcm interface e C f control word registers 11 direct c/i bits monitoring table 6-3. memory map: spi address (hex) function write registers default content when read 5det* pins control register. see section 5.7. 90 idem 6 normal sh-pots gci downstream c/i bits (b7-2): see sh-pots, excluding the ae bits. ff (non-active) idem 7 pcmclk clock frequency: the user must program the applied clock frequency at pcmclk pin as a multiple of 512 khz. program b7-4 = b3-0: 1 x 512 to 15 x 512 write 0001 to 1111 16 x 512 write 0000 44 (2048 khz) idem 8pcm in delay versus frame rising edge for line 0 per byte (b6-0: channel 0 C 127), default is 0 bytes. b7 is always = 0. 00 idem 9pcm out delay versus frame rising edge for line 0 per byte (b6-0: channel 0 C 127), default is 0 bytes. activation of the channel = b7, default = 0 = deactivated. 00 idem a pcm delay versus frame rising edge for line 0 per bit, default is b7-5 = 0; b4 = 1/2 clock period only for pcm out , other bits are for expansion and should be programmed 0. 00 (no shift) idem bpcm in delay versus frame rising edge for line 1 per byte (b6-0: channel 0 C 127), default is 1 byte. b7 is always = 0. 01 idem cpcm out delay versus frame rising edge for line 1 per byte (b6-0: channel 0 C 127), default is 1 byte. activation of the channel = b7, default = 0 = deactivated. 01 idem 6-11 MS140132KT detailed programming description: programming the pcm interface registers 0 to 4 and higher then 11 are for internal use only. writing to these registers may put the system into an undefined mode. 352*5$00,1*7+(3&0,17(5)$&( the pcm interface consists of inputs pcmclk, frame, pcm in , and output pcm out . pcmclk controls the internal operation of the pcm interface and shifts/latches the pcm data from pcm in in the interface on its falling edge, and sends the pcm data onto pcm out * on its rising edge. the data is read/written in the b-channels of the gci interface via the control block. frame is an 8-khz frame-sync pulse. its rising edge determines the beginning of the pcm data transfer out of pcm out and into pcm in . a register in the interface block defines the shift between this frame signal and the corresponding pcm channel. default values are as defined in the interface block register map. the frame pulse is one or more pcmclk periods long, with timing relationships as specified in figure 6-10. the pcm out open drain output buffer is enabled with reference to the rising edge of frame or the rising edge of pcmclk, depending on whichever comes later, and the first bit clocked out is the pcm sign bit. the following 7 rising edges of pcmclk shift out the remaining 7 bits, msb first. default compression of pcm data is a-law as defined in the codsp core. the pcm out output is disabled by the falling edge of pcmclk following the eighth rising edge. a rising edge of the frame will cause pcm data at pcm in to be latched after the last of the next 8 falling edges of pcmclk. see register 8-d for a description of how the activation and time delay can be programmed. figure 6-10 is an example of the default timing and programming a different setup. d pcm delay versus frame rising edge for line 1 per bit, default is b7-5 = 0; b4 = 1/2 clock period only for pcm out , other bits are for expansion and should be programmed 0. 00 (no shift) idem e control word channel 0. see section 6.4.2. 40 idem f control word channel 1. see section 6.4.2. 40 idem 11 na. remark: writing to this register may put the system into an undefined mode. ff normal gci upstream c/i bits (b7-2): see the ms140131kt datasheet. some bits can be sent to outputs det* . bits 1-0 are always high. table 6-3. memory map: spi (continued) address (hex) function write registers default content when read MS140132KT 6-12 detailed programming description: memory map of the codsp 0(025<0$32)7+(&2'63 global memory map and memid definitions: ? all addresses can be read and written, though writing to locations or individual bits which are not described here may result in unpredictable behavior. ? the default parameter and coefficient values that are used at startup and after reset are listed in the following tables. ? the memory block to be accessed is given as part of the read or write command (see above) as the b bits in the command byte. ? the control registers of the sh-pots system, accessed via the spi, are organized in a number of memory blocks. within each block, a number of addresses are used directly to control the operation of specific functions of the sh-pots system. figure 6-10. timing example of pcm interface frame pcmclk pcm out pcm in dont care high impedance 7 6543 2107 6543 210 7 6543 2107 6543 210 default timing pcm interface frame pcmclk pcm out pcm in dont care high impedance 7 6543 210 7 6543 210 7 6543 210 7 6543 210 timing example pcm interface: idl 10-bit mode timing note: default values + program reg. a = 20 and d = 60 for timing shift program reg. 9 = 80 for activation line 0 program reg. c = 81 for activation line 1. 6-13 MS140132KT detailed programming description: data ram memid = 2 '$7$5$030(0,' table 6-4. memory map for codsp memid memory start address memory contents 2 data ram 0x 02 0000 c-code read/write data c-code stack region c-code irq stack region 4 coprocessor coef ram 0x 04 0000 filter coefficients 5 shared ram 0x 05 0000 data packet buffers label vectors, fifo control table 6-5. data ram: memory map address 1514131211109876543210 00 (0x0000) bbs0 bsa0 bs0 br0 tst0 sh0 01 (0x0001) bbs1 bsa1 bs1 br1 tst1 sh1 02 (0x0002) 03 (0x0003) tx gain 0 04 (0x0004) tx gain 1 05 (0x0005) rx gain 0 06 (0x0006) rx gain 1 07 (0x0007) dzd1 dzd0 08 (0x0008) td1 td0 09 (0x0009) curlim_rlarge curlim_threshold 10 (0x000a) rw ril rm rf 11 (0x000b) ringing_dc_offset ringing_amplitude 12 (0x000c) ringing_off_period ringing_on_period 13 (0x000d) lbo 14 (0x000e) rtdac_thresholdlow rtdac_thresholdhigh 15 (0x000f) rtdac_debouncetime rtdac_gaptime 16 (0x0010) alarmreg 17 (0x0011) idc0 idc1 18 (0x0012) iac0 19 (0x0013) iac1 20 (0x0014) tg1 tg0 ms1 ms0 21 (0x0015) testtone_ampl1_l0 22 (0x0016) testtone_ampl1_l1 23 (0x0017) testtone_ampl2_l0 24 (0x0018) testtone_ampl2_l1 MS140132KT 6-14 detailed programming description: lbo register note: bit positions and memory locations not documented must not be changed. /%25(*,67(5 this register controls various loopback modes, as well as the routing of the gci b channels to or from the physical line analog channels. the bits are codes as shown in table 6-6. 25 (0x0019) testtone_freq1_l0 26 (0x001a) testtone_freq1_l1 27 (0x001b) testtone_freq2_l0 28 (0x001c) testtone_freq2_l1 29 (0x001d) acg 30 (0x001e) sleep2 pd1 pd0 rzd1 rzd0 sleep1 31 (0x001f) dialp_sattxlevel 32 (0x0020) dialp_debtime table 6-6. lbo register description mode d2 d1 d0 gci side analog side normal 0 0 0 tx(0) -> b1up tx(1) -> b2up b1down -> rx(0) b2down -> rx(1) simplex loop b2 0 0 1 tx(0) -> b1up b2down -> b2up b1down -> rx(0) tx(1) -> rx(1) simplex loop b1 0 1 0 b1down -> b1up tx(1) -> b2up tx(0) -> rx(0) b2down -> rx(1) simplex loop b1 and b2 0 1 1 b1down -> b1up b2down -> b2up tx(0) -> rx(0) tx(1) -> rx(1) duplex loopback 1 0 0 b2down -> b1up b1down -> b2up tx(0) -> rx(1) tx(1) -> rx(0) reserved 101 reserved 110 swap mode 1 1 1 tx(0) -> b2up tx(1) -> b1up b1down -> rx(1) b2down -> rx(0) note: bndown: gci b channel 1 or 2, downstream direction. bnup: gci b channel 1 or 2, upstream direction. tx(m): analog transmit signal (upstream direction), line 1 or 2. rx(m): analog receive signal (downstream direction), line 1 or 2. table 6-5. data ram: memory map (continued) address 1514131211109876543210 6-15 MS140132KT detailed programming description: alarm bits $/$50%,76 ? after initialization (e.g., due to a hardware reset), the codsp itself will make the upstream alarm bit active, and set the alarmreg with an initrequest value (i.e., 1xx). the alarm bit will remain active until the initrequest is cleared by the pcm/spi supervisor (indicating that the supervisor has done the necessary reinitialization of system parameters). ? in order to check the contents of the alarmreg, execute the following pcm/spi command: readrequest ( memid=2, add=0x0010 ); this results in a four-nibble value; e.g., 0xabgd, read by the supervisor. ? in order to clear the initrequest alarm, in principle, one must only clear one bit. therefore, the supervisor should execute the following commands: newvalue = "0xabgd" and "0xfffb"; writerequest ( memid=2, add=0x0010, newvalue ); ? note that the other bits in the alarm register are updated by the dsp at a 8 khz rate, and that they are only used by the pcm/spi supervisor; therefore, the other bits might also be overwritten for one cycle, clearing all bits (inclusive the initrequest bit) in one command: writerequest ( memid=2, add=0x0010, 0x0000 ); 0($1,1*$1''()$8/79$/8(62)7+( 3$5$0(7(56 table 6-7. data ram: description and default values name (note 1) address position description mapping default sh0, sh1 00, 01 0 shlic test mode control bit 0: normal mode 1: test mode 0 (normal) tst0, tst1 00, 01 1 shlic test switch control bit 0: open switch 1: closed switch 0 (open) br0, br1 00, 01 2 shlic battery reversal control bit 0: non-reversed 1: reversed 0 (non rev.) bs0, bs1 00, 01 3 shlic battery selection control bit for nonact_x variant 0: bats selection l 1: batr selection h 0 (nonact_l) bsa0, bsa1 00, 01 4 shlic battery selection control bit for actadsi_x variant 0: bats selection l 1: batr selection h 0 (actadsi_l) bbs0, bbs1 00, 01 6:5 shlic battery selection control bit for actrng_sph_x variant 0 = 00:bats l 1 = 01:batr h 2 = 10:bats + bias la 3 = 11:batr + bias ha 0 (actrng_sph_l) MS140132KT 6-16 detailed programming description: meaning and default values of the parameters tx_gain_0 tx_gain_1 03 04 15:0 gain factor in tx direction for line0 and line1 320 (0 db) rx_gain_0 rx_gain_1 05 06 15:0 gain factor in rx direction for line0 and line1 384 ( C 7db) dzd1, dzd0 07 1:0 disable digital z co path 0: enable 1: disable 1 (disabled) td1, td0 08 1:0 disable tx path at pdm level 0: enable 1: disable 0 (enabled) curlim_threshold 09 7:0 current limitation threshold parameter val = 0 ... 127 unit = 0.63 ma (eq = 0 ... 80 ma) 51 (32 ma) curlim_rlarge 09 15:8 current limitation rlarge resistance parameter (internal resistance) val = 0 ... 210 unit = 47 (eq = 0 ... 10 k w ) 64 (3 k w ) rf 10 1:0 ringing frequency 0 = 00: 16 hz 1 = 01: 20 hz 2 = 10: 25 hz 3 = 11: 50 hz 3 (50 hz) rm 10 2 ringing mode 0: on/off mode 1: burst mode 0 (on/off) ril 10 3 enable interleaved ringing 0: non-interleaved 1: interleaved 1 (interleaved) rw 10 5 ringing waveform 0: sine wave 1: trapezoidal wave 0 (sine) ringing_amplitude 11 7:0 amplitude of ringing signal val = 0 ... 255 unit = 194 mv rms 255 (max ampl) ringing_dc_offset 11 15:8 dc offset of ringing signal (between a and b wire) val = 0 ... 255 unit = 250 mv 0 (no offset) ringing_on_period 12 7:0 length of active ringing phase to be used in burst mode val = 0 ... 255 unit = 32 ms 32 (1 s) ringing_off_period 12 15:8 length of silent ringing phase to be used in burst mode val = 0 ... 255 unit = 32 ms 96 (3 s) lbo 13 3:0 gci loopback register (encoding see below) val = 0 ... 15 0 (no loop) rtdac_thresholdhigh 14 7:0 threshold level high during ringing val = 0 ... 255 unit = 1.6 ma 27 (43.2 ma) rtdac_thresholdlow 14 15:8 threshold level low during ringing val = 0 ... 255 unit = 1.6 ma 7 (11.2 ma) rtdac_gaptime 15 7:0 gaptime during rtdac peak detection val = 0 ... 255 unit = 125 s 10 (1.25 ms) table 6-7. data ram: description and default values (continued) name (note 1) address position description mapping default 20 log tx-gain_* 320 C7 + 20 log rx-gain_* 384 6-17 MS140132KT detailed programming description: meaning and default values of the parameters notes: 1. parameter names with 0 or 1 at the end refer to the analog line0 or line1. 2. in low power applications: recommended program value is sleep 1 = 5 combined with sleep 2 = 3 will save power consumption when only one line off-hook. rtdac_debouncetime 15 15:8 deb. time during rtdac val = 0 ... 255 unit = 125 s 240 (30 ms) alarmreg 16 2:0 alarm status register (encoding) val = 0 ... 7 4 (initreqst) idc1 17 7:0 dc line current of line1, sampled at 2 khz val = 0 ... 127 unit = 0.63 ma 0 idc0 17 15:8 dc line current of line0, sampled at 2 khz val = 0 ... 127 unit = 0.63 ma 0 iac0 18 15:0 ac line current of line0, sampled at 8 khz unit = 215/1.6 v @ tx 0 iac1 19 15:0 ac line current of line1, sampled at 8 khz unit = 215/1.6 v @ tx 0 tg1, tg0 20 3, 2 tone generator control bit for line1 and line0 0 : do not add tone 1 : add tone 0 (no tone) ms1, ms0 20 1, 0 mute speech control bit for line1 and line0 0 : pass speech 1 : mute speech 0 (no mute) testtone_ampl1_l0 testtone_ampl1_l1 21 22 7:0 amplitude of first sine for line0 and line1 val = 0 ... 255 63 (0 dbm) testtone_ampl2_l0 testtone_ampl2_l1 23 24 7:0 amplitude of second sine for line0 and line1 val = 0 ... 255 63 (0 dbm) testtone_freq1_l0 testtone_freq1_l1 25 26 15:0 frequency of first sine for line0 and line1 unit = 250 hz/256 1024/256 (1 khz) testtone_freq2_l0 testtone_freq2_l1 27 28 15:0 frequency of second sine for line0 and line1 unit = 250 hz/256 512/256 (500 hz) acg 29 7:0 rx amplitude correction for z co synthesis val = 0 ... 255/128 103/128 (600 w ) pd1, pd0 30 11:10 power denial mode line1 1 = enable 0 = disable 0 (disable) sleep2 (note 2) 30 13:12 low power activation 00 = inactive 11 = active 00 active sleep1 (note 2) 30 2:0 sleep factor to be used when one line inactive val = 0 ... 7 eq = 0 ... 70% sleepy 0 (0% sleep) rzd1, rzd0 30 4:3 disable analog z co path 0: enable 1: disable 0 (enabled) dialp_sattxlevel 31 15:0 tx saturation level to be used for dial pulse detection unit = 48.83 v @ tx 8192 (400 mv) dialp_debtime 32 15:0 debounce time to be used for dial pulse detection unit = 125 s 40 (5 ms) table 6-7. data ram: description and default values (continued) name (note 1) address position description mapping default MS140132KT 6-18 detailed programming description: coprocessor coefficient ram memid = 4 &2352&(6625&2()),&,(175$03 0(0,' access is similar to that of the data ram parameters. note, however, that the pcm/spi commands work with 2-byte values whereas the memory contains only 3-nibble values. because all values are <12, 0>, the most significant nibble of the 2-byte pcm/spi value will be a sign-extension of the 12-bit value. in the case of a readrequest; the most significant nibble of a writerequest will be neglected. table 6-8. coprocessor coefficient ram: memory map address11109876543210 00 (0x0000) rx32kfilter coefficient : r0 01 (0x0001) r1 02 (0x0002) r4 03 (0x0003) s1 04 (0x0004) s2 05 (0x0005) r2 06 (0x0006) r3 07 (0x0007) r5 08 (0x0008) s3 09 (0x0009) s4 10 (0x000a) m0 11 (0x000b) m1 12 (0x000c) u0 13 (0x000d) u1 14 (0x000e) hyb16kfilter coefficient : h0 15 (0x000f) h1 16 (0x0010) h2 17 (0x0011) h3 18 (0x0012) a0 19 (0x0013) c5 20 (0x0014) b0 21 (0x0015) tx32kfilter coefficient : t0 22 (0x0016) t1 23 (0x0017) t8 24 (0x0018) q1 25 (0x0019) q2 26 (0x001a) t2 27 (0x001b) t3 28 (0x001c) t9 6-19 MS140132KT detailed programming description: meaning and default values of the parameters 0($1,1*$1''()$8/79$/8(62)7+( 3$5$0(7(56 29 (0x001d) q3 30 (0x001e) q4 31 (0x001f) t4 32 (0x0020) t5 33 (0x0021) t10 34 (0x0022) q5 35 (0x0023) t6 36 (0x0024) t7 37 (0x0025) t11 38 (0x0026) q6 39 (0x0027) q7 40 (0x0028) c2 41 (0x0029) c3 42 (0x002a) zcotxfilter coefficient : ftx 43 (0x002b) ap 44 (0x002c) nan 45 (0x002d) constants : hlf 46 (0x002e) one_eight table 6-9. coprocessor coefficient ram: description and default values name address position description mapping default r0 00 11:0 rx filter coefficient unit = intval / 512 int96 r1 01 11:0 rx filter coefficient unit = intval / 512 int78 r4 02 11:0 rx filter coefficient unit = intval / 512 int96 s1 03 11:0 rx filter coefficient unit = intval / 512 int642 s2 04 11:0 rx filter coefficient unit = intval / 512 int263 r2 05 11:0 rx filter coefficient unit = intval / 512 int256 r3 06 11:0 rx filter coefficient unit = intval / 512 int303 r5 07 11:0 rx filter coefficient unit = intval / 512 int256 s3 08 11:0 rx filter coefficient unit = intval / 512 int746 s4 09 11:0 rx filter coefficient unit = intval / 512 int450 table 6-8. coprocessor coefficient ram: memory map (continued) address11109876543210 MS140132KT 6-20 detailed programming description: meaning and default values of the parameters m0 10 11:0 rx filter coefficient unit = intval / 512 int512 m1 11 11:0 rx filter coefficient unit = intval / 512 int512 u0 12 11:0 rx filter coefficient unit = intval / 512 int0 u1 13 11:0 rx filter coefficient unit = intval / 512 int0 h0 14 11:0 echo cancelling coefficient unit = intval / 512 int109 h1 15 11:0 echo cancelling coefficient unit = intval / 512 int2 h2 16 11:0 echo cancelling coefficient unit = intval / 512 int8 h3 17 11:0 echo cancelling coefficient unit = intval / 512 int32 a0 18 11:0 echo cancelling coefficient unit = intval / 512 int127 c5 19 11:0 echo cancelling coefficient unit = intval / 512 int512 b0 20 11:0 echo cancelling coefficient unit = intval / 512 int157 t0 21 11:0 tx filter coefficient unit = intval / 512 int48 t1 22 11:0 tx filter coefficient unit = intval / 512 int37 t8 23 11:0 tx filter coefficient unit = intval / 512 int48 q1 24 11:0 tx filter coefficient unit = intval / 512 int728 q2 25 11:0 tx filter coefficient unit = intval / 512 int439 t2 26 11:0 tx filter coefficient unit = intval / 512 int390 t3 27 11:0 tx filter coefficient unit = intval / 512 int492 t9 28 11:0 tx filter coefficient unit = intval / 512 int390 q3 29 11:0 tx filter coefficient unit = intval / 512 int573 q4 30 11:0 tx filter coefficient unit = intval / 512 int227 t4 31 11:0 tx filter coefficient unit = intval / 512 int64 t5 32 11:0 tx filter coefficient unit = intval / 512 int128 t10 33 11:0 tx filter coefficient unit = intval / 512 int64 q5 34 11:0 tx filter coefficient unit = intval / 512 int442 t6 35 11:0 tx filter coefficient unit = intval / 512 int384 t7 36 11:0 tx filter coefficient unit = intval / 512 int768 t11 37 11:0 tx filter coefficient unit = intval / 512 int384 q6 38 11:0 tx filter coefficient unit = intval / 512 int962 q7 39 11:0 tx filter coefficient unit = intval / 512 int458 c2 40 11:0 tx filter coefficient unit = intval / 512 int512 c3 41 11:0 tx filter coefficient unit = intval / 512 int512 ftx 42 11:0 z co tx filter coefficient unit = intval / 512 int237 table 6-9. coprocessor coefficient ram: description and default values (continued) name address position description mapping default 6-21 MS140132KT detailed programming description: shared memory memid = 5 6+$5('0(025<30(0,' note: bit positions and memory locations not described here must not be changed. ap 43 11:0 z co tx filter coefficient unit = intval / 512 int0 nan 44 11:0 z co tx filter coefficient unit = intval / 512 int0 hlf 45 11:0 constant definition unit = intval / 512 int256 one_eight 46 11:0 constant definition unit = intval / 512 int64 table 6-10. shared memory: memory map address15 14 13 12 1110987 6 543210 85 (0x0055) vlm ht deb mf mm 86 (0x0056) spido spidi spisk spics spise rbd sr* sr* sr* sr* 87 (0x0057) hsd_thresholdhigh hsd_thresholdlow 88 (0x0058) rtd_thresholdhigh rtd_thresholdlow 89 (0x0059) meteringdutycycle 90 (0x005a) zcoshalfa3 zcoa2 rxd* alo* sleep* 91 (0x005b) rzco zcogamma zcoalfa3 94 (0x005e) tl table 6-9. coprocessor coefficient ram: description and default values (continued) name address position description mapping default MS140132KT 6-22 detailed programming description: meaning and default values of the parameters 0($1,1*$1''()$8/79$/8(62)7+( 3$5$0(7(56 table 6-11. shared memory: description and default values name address position description mapping default vlm 85 14:11 metering amplitude (unit value = depending on z co ) val = 0 ... 15 3 ht 85 10:9 hsd debounce time 0 = 00: 8 ms 1 = 01 : 24 ms 2 = 10 : 16 ms 3 = 11: 64 ms 2 (16 ms) deb 85 8 rtd debounce time 0 : 0 ms 1 : 30 ms 1 (30 ms) mf 85 4 metering frequency 0 : 12 khz 1 : 16 khz 1 (16 khz) mm 85 3 metering mode 0 : burst mode 1 : on/off mode 1 (on/off) spido 86 15 spi d out port 0 spidi 86 14 spi d in port 0 spisk 86 13 spi sk port 0 spics 86 12 spi cs port 0 spise 86 11 spi port selection 0 rbd 86 10 disable automatic ring activation of spick and spick 1 = disabled 0 = enabled 0 (enabled) sr (note 1) 86 5:4 1:0 software resets of sid1, sid0, cp, gci 1 = reset block 0 = no reset 0 soft resets (note 2) 86 5:0 reset ability of hw blocks (sid0, sid1, mrt, ls, cp, gci) 0: no reset 1: reset block 0 (no reset) hsd_thresholdhigh 87 13:7 hsd high threshold val = 0 ... 127 unit = 0.63 ma = 0 ... 80 ma 16 (10 ma) hsd_thresholdlow 87 6:0 hsd low threshold val = 0 ... 127 unit = 0.63 ma = 0 ... 80 ma 10 (6.3 ma) rtd_thresholdhigh 88 13:7 rtd high threshold val = 0 ... 127 unit = 0.63 ma = 0 ... 80 ma 16 (10 ma) rtd_thresholdlow 88 6:0 rtd low threshold val = 0 ... 127 unit = 0.63 ma = 0 ... 80 ma 10 (6.3 ma) meteringdutycycle 89 15:8 length of the metering burst to be used in burst metering mode val = 0 ... 255 unit = 2 ms = 0 ... 510 ms 150 (300 ms) 6-23 MS140132KT detailed programming description: meaning and default values of the parameters notes: 1. examples of other z co parameters are listed in table 4-4. otherwise, contact a motorola sales office. 2. do not change these values. zcoshalfa3 90 15:1 central office impedance parameter (note 1) 0 (600 w ) zcoa2 90 13:7 central office impedance parameter (note 1) 0 (600 w ) rxd (note 1) 90 6 rxdisable at input of analog part 0: enabled rx path 1: disable rx path 0 (enabled) alo (note 2) 90 4 analog loopback at pdm 0: disabled loop 1: enable loop 0 (disabled) sleep (note 2) 90 2:0 sleep factor actually used by the processor val = 0 ... 7 = 0 ... 70% sleepy 0 (0% sleep) rzco 91 11:8 central office impedance parameter (note 1) 3 (600 w ) zcogamma 91 7:4 central office impedance parameter (note 1) 0 (600 w ) zcoalfa3 91 3:0 central office impedance parameter (note 1) 0 (600 w ) tl 94 1:0 transcode law selection 0 = 00: a law 1 = 01: m law 2 = 10: linear 0 (a-law) table 6-11. shared memory: description and default values (continued) name address position description mapping default MS140132KT 7-1 6(&7,21 0(&+$1,&$/63(&,),&$7,216 0&3$&.$*(',0(16,216 ???? ???? 44 1 34 33 11 12 22 23 view y l n ( 2) c view aa (k) e (z) view aa f u section abab j d base metal plating ab ab view y s lm m 0.20 (0.008) n t 2x r m 3x b1 v1 b lm 0.2 (0.008) t v a1 s1 a s n lm 0.2 (0.008) hn 4x 4x 11 tips t h 4x ( 3) 4x 0.1 (0.004) t 1 r1 (w) c2 c1 s 0.05 (0.002) 0.25 (0.010) gage plane 40x g x x=l, m, n c l rotated 90 clockwise dim min max min max inches millimeters a 10.00 bsc 0.394 bsc a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b2 5.00 bsc 0.197 bsc c 1.60 0.063 c1 0.05 0.15 0.002 0.006 c2 1.35 1.45 0.053 0.057 d 0.30 0.45 0.012 0.018 e 0.45 0.75 0.018 0.030 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc j 0.09 0.20 0.004 0.008 k 0.50 ref 0.020 ref r1 0.09 0.20 0.004 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref 0 7 0 7 0 0 12 ref 12 ref 12 ref 12 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums l, m and n to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane t. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.53 (0.021). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). 1 2 3 seating plane fu suffix tqfp package case 824d-02 7-2 MS140132KT mechanical specifications: mc1420233 package dimensions 0&3$&.$*(',0(16,216 a1 1 15 14 28 b s a m 0.025 b s c m 0.25 b m seating plane a notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusions. 4. maximum mold protrusion 0.015 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 l 0.41 0.90 q 0 8 l q c pin 1 ident a b d e h e 0.10 c dw suffix soic package case 751f-05 MS140132KT 7-3 mechanical specifications: mc1420233 package dimensions 5(&200(1'('3$'/$<287)25 /($'74)30& b a solder pad size: w = 0.55 mm x l = 2.0 mm solder pad pitch: 0.8 mm (center to center) toe to toe dimension: a = 14.2 mm x b = 14.2 mm figure 7-1. recommended pad layout for 44-lead tqfp mc1420233 MS140132KT/d digital dna is a trademark of motorola, inc. how to reach us: usa/europe/locations not listed: motorola literature distribution: p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1 minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. 852-26668334 technical information center: 1-800-521-6274 home page: http://motorola.com/semiconductors/ ? motorola, inc., 2001 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. typical parameters can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorol a products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola pr oduct could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affi liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim al leges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. |
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